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★ 10/22第一次小考，詳細資訊請見「總課程網頁」

★ 作業二請於10/22 14:20前繳交，助教會到教室親自收取

★ 11/6 15:30--18:00 Verilog 教學，請同學們務必參加

★ 11/12 溫書假，停課一次

★ 作業三請於11/13 15:30前繳交給各教室監考助教

★ 11/13 期中考，請同學們及早準備

★ 12/07第二次小考，詳細資訊請見「總課程網頁」

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★ 0. Syllabus of the Course <2009/9/17>

★ 1. Introduction: Number System and Conversion (script) <2009/9/17>

★ 2. Boolean Algebra (script) (Dual examples) <2009/9/24>

★ 3. Boolean Algebra (Continued) (script) (Validity example) <2009/9/25>

★ 4. Application of Boolean Algebra/Minterm and Maxterm Expansions (script) <2009/10/02>

★ 5. Karnaugh Maps (script) <2009/10/08>

★ 7. Multi-Level Gate Circuits NAND and NOR Gates (script) <2009/10/15>

★ 8. Combinational Circuit Design and Simulation Using Gates (script) <2009/10/23>

★ 9. Multiplexers, Decoders, and Programmable Logic Devices (script) (Notes in class) <2009/10/29>

★ 11. Latches and Flip-Flops (script) <2009/11/19>

★ 12. Registers and Counters (script) (Notes in class) <2009/11/27>

★ 13. Analysis of Clocked Sequential Circuits (script) <2009/12/04>

★ 14. Derivation of State Graph and Tables (script) (Notes in class) <2009/12/10>

★ 15. Reduction of State Tables State Assignment (script) <2009/12/18>

★ 15.8. Guidelines for State Assignment (script) <2009/12/18>

★ 16. Sequential Circuit Design (script) <2009/12/17>

★ 18. Circuits for Arithmetic Operations (script) <2009/12/31>

★ Some Design Examples (script) <2009/12/31>

★ 6. Quine-McCluskey Method (script) <2010/01/07>

★ Logic Design:Current Status and Future Study<2010/01/07>